Ultraflex


In Part 3a, we discussed the possibility of a purpose-driven Compute Node based on the Torrenza initiative for the Future Storage system.  This expansion node made use of Hypertransport as a “glue” between the base storage compute node and the expansion node (of computation or I/O flavours) that could be added.  The advantages of that topology were simple:  hot add support for additional processing power, additional I/O bandwidth within the system, and additional computing power for the array OS (which we’ll cover in a later article).  In this overview, we’ll take a look at another variation on an expansion node: an I/O expansion node that will add additional front-end ports and/or functionality to the base system.  We will be referencing the diagram below. (Apologies in advance for the image shearing off in the lower right hand corner).

Hypertransport I/O Expansion Topology

Hypertransport I/O Expansion Topology

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EMC CX4 is ALIVE!

by dave on August 6, 2008


Which memory locations can be cached by which ...Image via Wikipedia

Is it just me or have we been waiting for this for a while? 😉  Today is officially the EMC Clariion CX4 public GA (general availability) date.  Good news: they’re shipping TODAY!  No paper launches, folks…this is immediate availability.  The other good news: you get to do more with your storage; faster, cheaper, stronger, more flexible, etc.  Let me rip through some highlights for you:

a.) Cache and SP Processor increases.  Across the board, processor “speeds” and cache sizes have been increased.  Now, this may appear somewhat odd in that the CX4-120, for example, only has two dual core 1.2ghz processors, but, when you consider that the onboard L2 cache is greater in size (and Woodcrest processors were HANDILY more powerful than the older Nocona Xeons), it actually has more innate processing power than the previous generation processors.  Cache sizes, when coupled with the 64 bit FLARE OS for the array, allow for better allocation and utilization within the array. 

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