Video: Cisco C200 M1 Overview

by Dave Graham on January 22, 2010

Cisco Systems, lnc.
Image via Wikipedia

I finally received some new servers in the Atmos lab and…well, I thought I’d share with you!!!  These are Cisco C200 M1 servers and they’re loaded out in the following config:

ProcessorsIntel Xeon 5520 (2.27Ghz quad cores w/Hyperthreading)

Memory: 4Gb DDR3 ECC/Registered x 12 for a total of 48Gb memory

NICs: Dual ServerEngines Gigabit Ethernet NICS + dedicated IPMIKVM-over-IP NIC

Enjoy the video!!!!

UPDATE:  YouTube does SD (standard definition) processing first and HD processing second.  if it looks terrible now, just wait and it’ll look better.

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Future Storage Systems: A pause in workflow

by Dave Graham on October 17, 2008

Since I started this article series, I’ve had the awesome opportunity to have my ideas (well, some of the early articles at least) reviewed by person(s) who deal with the actual infrastructure of storage systems day in, day out.  The benefit of such peer review is that you get to learn at the symbolic “feet” of the masters and discover flaws, omissions, and understated features that need to be understood and incorporated.  This post is dedicated to some of those discussions and, where applicable, my understanding of how the FSS either incorporates or misses the boat.

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In the previous two articles on the Future Storage System (FSS), I took a general look at a basic storage system architecture (Part 1) and then went a bit deeper into some of the more interesting bits of that system from a platform standpoint (Part 2).  In this article, I want to dive a bit deeper into how I envision nodes to be building blocks for additional capabilities and processing directives.  I will be referencing the image below as part of this article.

Hypertransport Node Expansion (detailed)

Hypertransport Node Expansion (detailed)

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Why wouldn’t the following work? (Future Storage System: Part 1)

October 7, 2008

So, I’ve been toying around with this in my mind for some time.  Essentially, I’ve tried to understand the basic “Storage Processor” limitation of current storage systems and propose an admittedly simplistic design to get around some of the difficulties.  The biggest hurdle, in my mind, is to have cache coherency, low latency memory access [...]

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Snoop Filters and the Tyan S5397

September 26, 2008

Just to add to the ever-growing information data base on the excellent Tyan S5397.
If you seem to be having problems with reported memory bandwidth in your favourite worthless synthetic benchmark or reality-based simulation workload, try disabling the Snoop Filter in the bios.

Remember, the Intel Xeon processors use a different set of prefetch schedulers than standard [...]

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