Posts tagged as:

Central processing unit


In developing the Future Storage System series, I have been trying to take a part of my excitement for storage technologies and overlay them with systems/platform technology.  Typically, the storage industry lags on the platform development side of the house (mostly out of necessity).  So, part of looking at the Future Storage System was to take into consideration that in the basic design, some of the more current technologies could and should be used to enable “forward” thinking.  That’s why you see such a heavy emphasis on Torrenza, Hypertransport, and integrated memory controllers.  With the exception of Torrenza, each of the other aspects of system design have a rich history.  Hypertransport, arguably, has been an outlier on the bus technology side, but it’s capabilities and industry support are unparalleled.  Integrated memory controllers, while “nothing new” (DEC Alpha, anyone?) really came to the for when AMD introduced them as part of the Athlon series of processors.  Today, I’d like to toss another wrinkle into the “platform meets storage” discussion by including another developing technology: the GPU (Graphical Processing Unit).

[click to continue…]

{ 4 comments }

Search Term Reviews: October 23rd Edition

by dave on October 23, 2008


Given that I’m trying to get back into a regular schedule of posting (and the relative frequency of “interesting” search phrases that lead people here), I hereby present the October 23rd Search Term Edition post!  In case you missed last week’s, you can find it here.

With further ado, let’s get started.

Search Term #1:  AX4-5

[click to continue…]

{ 0 comments }


In the previous two articles on the Future Storage System (FSS), I took a general look at a basic storage system architecture (Part 1) and then went a bit deeper into some of the more interesting bits of that system from a platform standpoint (Part 2).  In this article, I want to dive a bit deeper into how I envision nodes to be building blocks for additional capabilities and processing directives.  I will be referencing the image below as part of this article.

Hypertransport Node Expansion (detailed)

Hypertransport Node Expansion (detailed)

[click to continue…]

{ 2 comments }