AMD

Future Storage Systems: Part 3b – I/O Expansion Node

October 10, 2008

In Part 3a, we discussed the possibility of a purpose-driven Compute Node based on the Torrenza initiative for the Future Storage system.  This expansion node made use of Hypertransport as a “glue” between the base storage compute node and the expansion node (of computation or I/O flavours) that could be added.  The advantages of that […]

Share
<br />

Future Storage Systems: Part 3a – Node Expansion Overview

October 9, 2008

In the previous two articles on the Future Storage System (FSS), I took a general look at a basic storage system architecture (Part 1) and then went a bit deeper into some of the more interesting bits of that system from a platform standpoint (Part 2).  In this article, I want to dive a bit […]

Share
<br />

Future Storage Systems: Part 2 – Detailed Node View

October 8, 2008

So, in my article yesterday, I gave a global view of a very simple storage system for the future. Since I LOVE this type of conjecture and theoretics (is that a word?), I decided to take this a step further and flesh out some of the other intricacies of the design.  Check out the image […]

Share
<br />

Why wouldn’t the following work? (Future Storage System: Part 1)

October 7, 2008

So, I’ve been toying around with this in my mind for some time.  Essentially, I’ve tried to understand the basic “Storage Processor” limitation of current storage systems and propose an admittedly simplistic design to get around some of the difficulties.  The biggest hurdle, in my mind, is to have cache coherency, low latency memory access […]

Share
<br />

Fun with nVidia’s Hybrid SLI

June 14, 2008

Image via Wikipedia
It’s always fun to bring in “extra-curricular” stuff that I do to my day job.  That being said, this one is strictly outside the scope of day-to-day work.  I recieved a very interesting bit of technology from nVidia that is designed to demo out their Hybrid SLI platform.  What is Hybrid SLI, you […]

Share
<br />