a.) The choice of AMD, while not necessarily obvious on the surface, is really tied to their implementation of Hypertransport for both system I/O as well as processor I/O. using cHT as well as ncHT throughout a system means that my economy of scale is ONLY limited by the amount of nodes I wish to attach. Additionally, it avoids some of the limitations of messaging limits (for example) on Infiniband.
b.) Torrenza further extends the platform by allowing hardware-dependent features to be added as needed (such as dedicated encryption, deduplication engines) directly into the system I/O bus without having to extensively remap I/O through bridge chips, etc. VERY cool technology. This also ties into the concept of using GPGPUs for these type of processes as well which, believe it or not, are a heck of a lot more powerful than FPGA asics that our bretheren @ 3Par and BlueArc use.

As far as drive counts are concerned, that’s really not an issue. I’ll pack them in where they make sense ? (40 x 2.5” is very good scale but sealed drive packs aren’t necessarily as effective (imho) as you portend them to be.) of note, I’m not a big fan of our 3U 15 drive DAEs either….

cheers,

Dave

Interesting article, just ran across it. In the article, you describe your 'future storage system'. What you have just described is the Intelligent Storage Element (ISE) – which is not future, it's present. Massive scale in minimum footprint, switched topology, both 2.5″ and 3.5″ drives. BTW, it's 40 2.5″ drives in 3U, not 30-36.

Keep up the good work.

a.) The choice of AMD, while not necessarily obvious on the surface, is really tied to their implementation of Hypertransport for both system I/O as well as processor I/O. using cHT as well as ncHT throughout a system means that my economy of scale is ONLY limited by the amount of nodes I wish to attach. Additionally, it avoids some of the limitations of messaging limits (for example) on Infiniband.
b.) Torrenza further extends the platform by allowing hardware-dependent features to be added as needed (such as dedicated encryption, deduplication engines) directly into the system I/O bus without having to extensively remap I/O through bridge chips, etc. VERY cool technology. This also ties into the concept of using GPGPUs for these type of processes as well which, believe it or not, are a heck of a lot more powerful than FPGA asics that our bretheren @ 3Par and BlueArc use.

As far as drive counts are concerned, that’s really not an issue. I’ll pack them in where they make sense ? (40 x 2.5” is very good scale but sealed drive packs aren’t necessarily as effective (imho) as you portend them to be.) of note, I’m not a big fan of our 3U 15 drive DAEs either….

cheers,

Dave

Interesting article, just ran across it. In the article, you describe your 'future storage system'. What you have just described is the Intelligent Storage Element (ISE) – which is not future, it's present. Massive scale in minimum footprint, switched topology, both 2.5″ and 3.5″ drives. BTW, it's 40 2.5″ drives in 3U, not 30-36.

Keep up the good work.